]> file package library use access after alias all assert begin block body bus component constant disconnect downto end exit function generate generic group guarded impure inertial is label linkage literal map new next null on open others port postponed procedure process pure range record register reject report return select severity signal shared subtype then to transport type unaffected units until variable wait when with note warning error failure in inout out buffer and or xor not else elsif loop bit bit_vector character boolean integer real time string severity_level positive natural signed unsigned line text std_logic std_logic_vector std_ulogic std_ulogic_vector qsim_state qsim_state_vector qsim_12state qsim_12state_vector qsim_strength mux_bit mux_vector reg_bit reg_vector wor_bit wor_vector